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Gated timer -- is there a way to do this?

timer gated

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#1 chuckb

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Posted 10 March 2014 - 12:56 PM

I would like use an FIOx input to gate the counting of a timer, which I can latch/read at a later time while it's still counting.  For example:


1) Timer0 is cleared to 0

2) FIO4 input goes high, which gates Timer0 to start incrementing at configured clock rate

3) time passes...

4) PC software has an internal event, queries Timer0 to get elapsed time since FIO4 input went high.

5) FIO4 input goes inactive low.

Process repeats...


Is there any way to accomplish this gating functionality?  The only way I can think of is to:

a)  Poll FIO4 waiting for it to go high

b)  Read System Timer (Mode 10) when it goes high

c)  PC software again reads System Timer upon internal event.


Step (a) above has two problems:

i)  Requires PC software to rapidly poll (invasive).  I would like to offload this tedious task to Labjack...

ii) Accuracy is reduced by command/response delay.


Is there a way to do this using existing Timer functionality (no polling).


#2 LabJack Support

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Posted 11 March 2014 - 10:19 PM

It looks like we may be able to add this feature to the T7.


For the U3 I think your best bet is to use the duty cycle measurement. It measures both the high-time and the low-time of a signal. High-time being the time between a rising edge and a falling edge. For your application you would only be interested in the high-time.

#3 chuckb

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Posted 31 March 2014 - 07:22 AM

Thanks for the reply.  For U3, duty cycle won't help since I want to query the HW timer value based upon a SW internal event (step #4) which precedes when the FIO4 input returns low (step #5).

What I have decided to try is Mode 14 (line to line).  I will use a separate FIOx output to loop-back into FIO5 (timer1), incurring the ~1msec FIOx output USB command delay/jitter penalty.


This I think will let me measure the time from when FIO4 goes high until a SW internal event...

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