Maximum Divisor (Timer Mode 7), Frequency Output
Posted 26 October 2006 - 06:20 AM
Posted 26 October 2006 - 10:47 AM
Posted 26 October 2006 - 11:57 AM
Posted 23 June 2015 - 06:55 AM
Hi, many combinations seems to be invalid. Can you please specify what combinations that works on the UE9?
I use the following setup and gets some combinations to work and some not.
For example tthe combination below should give about 45 Hz but the output is set to 5.7 Hz
Posted 23 June 2015 - 01:35 PM
The two valid clock bases are LJ_tc750KHZ (750 kHz) and LJ_tcSYS (system). The system clock is 48 MHz by default, and if the control power level is set to low (LJ_ioPUT_CONFIG, LJ_chCONTROL_POWER_LEVEL, value = 1) the system clock is lowered to 6 MHz. I would expect LJUD.TIMERCLOCKS.MHZ6_DIV (LJ_tc6MHZ_DIV) constant to cause an LJE_INVALID_PARAMETER error with the UE9.
Valid divisor values are 0-255, where 0 = 256. The same values apply for the frequency output value.
If you want a frequency output of about 45, set the timer clock base to 750 kHz with a 256 divisor (value = 0), then set your frequency output value to 32 (freq = (750000/256)/(2*32) = 45.7 Hz). The lowest frequency you can set is 5.7 Hz which you seem to be seeing.
To see the timer/counter constants that can be used with the UE9, refer to the time and counter pseudocode in the User's Guide.
Also, LJUD.CHANNEL.TIMER_COUNTER_PIN_OFFSET (LJ_chTIMER_COUNTER_PIN_OFFSET) does not apply to the UE9. Timer and counters always start on FIO0.
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